EDA技术与Verilog设计第六章课后习题部分答案.pptVIP

module wytest(reset,clk,in,out); input reset,clk,in; output out; reg out; reg[1:0] state,next_state; parameter s0=2d0,s1=2d1,s2=2d2,s3=2d3; always@(posedge clk) begin if(!reset) state=s0; else state=next_state; end always@(state or in) case(state) s0:if(in==1) next_state=s1; else next_state=s0; s1:if(in==0) next_state=s2; else next_state=s1; s2:if(in==0) next_state=s3; else next_state=s1; s3:if(in==1) next_state=s1; else next_state=s0; default:next_state=s0; endcase always@(state or in) case(state) s0:if(in==1) out=0; else out=0; s1:if(in