VHDL程序题.doc

1．以下是一位全加器的VHDL设计，试补充完整。 library ieee; --半加器设计 use ieee.std_logic_1164.all; entity h_adder is port (a, b : in std_logic; co, so : out std_logic); end h_adder; architecture fh1 of h_adder is begin so = not(a xor (not b)) ; co = a and b ; end architecture fh1; library ieee; --或门设计 use ieee.std_logic_1164.all; entity or2a is port (a,b: in std_logic; c: out std_logic); end or2a; architecture rtl of or2a is begin c= a or b after 10 ns; end rtlibrary ieee; --全加器设计 use ieee.std_logic_1164.all; entity f_adder IS port (ain,bin,cin : in std_logic; cout,sum : out std_logic ); end entity f_adder; architecture fd1 OF f_adder IS component h_adder port (a, b : in std_logic; co, so : out std_logic); end component; component or2a port (a,b: in std_logic; c: out std_logic); end component; signal d, e, f : std_logic; begin u1 : h_adder port map(a=ain, b=bin, co=d, so=e); u2 : h_adder port map (a=e, b=cin, co=f, so=sum); u3 : or2a port map (a=d, b=f, c=cout); end architecture fd1; 2．以下是含有使能端且具有同步清零的加减计数器的VHDL设计，试补充完整。 library ieee; use ieee.std_logic_1164.all; entity counter is port(updown,enable,clear,clk:in std_logic; q:out integer range 0 to 255); end counter; architecture a of counter is begin process(clk) variable cnt:integer range 0 to （7） ; variable direction: （8） ; begin if (updown=1) then direction:=1; else （9） end if; if(clkevent and clk=1) then if clear=0 then cnt:=0; else if enable=1 then （10） end if; end if; end if; q=cnt; end process; end a;  (7) 255 (8) integer (9) direction:= -1； (10) cnt:=cnt+direction  1．以下是8位分频器程序设计 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY PULSE IS PORT ( CLK : IN STD_LOGIC; D : IN STD_LOGIC_VECTOR (7 DOWNTO 0); FOUT : OUT STD_LOGIC ); END; ARCHITECTURE one OF PULSE IS SIGNAL FU