基于MIPS指令集的32位RISC处理器逻辑设计.docVIP

本 科 生 毕 业 论 文 题 目： 院 系： 专 业： 学生姓名： 学 号： 指导教师： 副教授 二〇〇年月 摘要 本文的首先概述了MIPS指令集的重要特征，为讨论CPU的具体设计奠定基础。本文设计的3个版本的CPU均实现了一个共包含59条指令的32位MIPS指令子集。 本文的主体部分首先详细描述了处理器各个独立功能模块的设计，为后续的整体设计实现提供逻辑功能支持。随后按照单周期、多周期、流水线的顺序，循序渐进的围绕着指令执行过程中需经历的五个阶段，详细描述了3个版本的处理器中各阶段的逻辑设计。在完成了各个版本的CPU的整体逻辑设计后，通过Quartus II时序仿真软件在所设计的CPU上运行了测试程序，测试输出波形表明了处理器逻辑设计的正确性。 本文还通过Quartus II 7.2中的Quartus II Time Quest Timing Analyzer软件，基于Altra公司的FPGA器件比较分析了所设计的3个版本CPU的性能。其中单周期CPU基于Altra公司的Cyclone III系列EP3C120F484C7器件综合的频率可达10.417MHz，而多周期CPU的综合频率可达12.935MHz，五级流水线CPU的综合频率可达12.376MHz。 关键词： Abstract CPU is a core component of computer system, which has been widely used in a variety of information devices in different areas of industry. Processor design and manufacturing technology is also one of the most important computer technologies nowadays. MIPS is one of the world-wide popular RISC processor. MIPS means “microprocessor without interlocked piped stages”. Its mechanism is to make full use of software to solve the data-related problem in the pipeline. Based on a detailed study of MIPS instruction set architecture, this paper describes the logic design of a MIPS-based 32-bit RISC processor in detail, which is developed with hardware description language VHDL in Quartus II 7.2. The design includes the following three versions of 32-bit RISC processor, the single-cycle version, the multi-cycle version and the 5-pipeline version. All the three versions have been tested in the Quartus II timing simulation software environment. A performance analysis of the three versions is given by the paper according to the timing simulation test results. First of all, the paper provides an overview of the important features of the MIPS instruction set, including the instruction format, instruction classification and the addressing mode, which lays the foundation of the following discussion about the specific logic design. A 59-instruction subset of 32-bit MIPS