EDA第五章VHDL设计进阶4-8节-子程序以后-定稿.pptVIP

LIBRARY IEEE; II、 8-3线优先编码器 例5-45 方法1 USE IEEE.STD_LOGIC_1164.ALL; --使用条件赋值语句实现 ENTITY encoder IS PORT( a,b,c,d,e,f,g,h:IN STD_LOGIC; out0,out1,out2:OUT STD_LOGIC); END encoder; ARCHITECTURE behave1 OF encoder IS --条件赋值方式 SIGNAL outvec:STD_LOGIC_VECTOR(2 WOWNTO 0); BEGIN outvec(2 DOWNTO 0)= “111”WHEN h=‘1’ ELSE “110”WHEN g=‘1’ ELSE “101”WHEN f=‘1’ ELSE “100”WHEN e=‘1’ ELSE “011”WHEN d=‘1’ ELSE “010”WHEN c=‘1’ ELSE “001”WHEN b=‘1’ ELSE “000”WHEN a=‘1’ ELSE “000”;