mealy和moore型状态机编程和测试.docxVIP

Mealy型?module?mealy(clock,l,p,state);??input?clock,l;??output?p,state;??reg?p;??reg?state;??parameter?high=1b1,?low=1b0;??initial??begin?state=low;?p=0;??end??always@(posedge?clock)?case?(state)???low:?if(!l)?begin?state=low;?p=0;?end?else?begin?state=high;??p=1;?end?high:?if(!l)?begin??state=low;??p=0;?end??else?begin?state=high;?p=0;?end??default:begin?state=low;?p=0;?end??endcase??endmodule?Mealy型测试模块：?`includeF:/verilog_homework/exercise_2/mealy/mealy.v?module?mealy_test;??reg?clk,l;??wire?q;??wire?state;??initial???clk=0;??always???#10?clk=~clk;?initial???begin?????????l=1b0;????#20l=1b1;