CMOS集成电路制造工艺介绍.ppt.ppt

CONT Poly 与金属之间或者扩散与金属之间的连接孔称为CONT 每个CONT的导通电阻大概是20欧姆左右，相对来说比较大，因此如果用于输出端连接，都会尽量地多打一些CONT，一般是要As more as possible VIA VIA 即通孔，是用于连接金属与金属之间的连接孔。 工艺上为了降低通孔的连接电阻，用钨栓作为连接介质。每个通孔的导通电阻大概为5欧姆左右。(RC01S) Metal 一般为AL工艺或铜工艺。 RC01S-HND 为5层金属铝铜工艺，第一层金属方块电阻为0.145欧姆，第2~第4层方块电阻为0.115欧姆，第5层方块电阻为0.035欧姆 瑞萨90nm process ---Cu 工艺 A typical 0.13um CMOS process flow RC01SHND 130nm Process 工艺流程示意图演示 instruction： P+ ：high density of P ion implant P- ：lower density of P ion implant P ： two implants,once P-, once P+ So did ：As+，As-，B+，B- …… P-Sub 1.1 Substrate: P-Si (Axis:100) 1.2 Oxide growth P-Sub SiO2 Method: 1) Dry oxidation 2) Wet oxidation Axis:100 1) Low interface trap density Nit(111)/Nit(100)~10 2) Higher surface carrier mobility μ(100) μ(111) P-Sub 1.3 Si3N4 deposition 1.4 photoresist covering P-Sub CVD deposition Photoresisit: positive negative P-Sub P+ 1.5 deep n-well formation mask1 P-Sub DNW UV 1.6 deep n-well implant mask DNW: 1) Improve substrate noise 1) Digital-analog separate 3) Back bias adjust P-Sub DNW 1.7 Select DNW region as operational object P-Sub DNW P-Sub DNW N-well P+ 1.9 N-well implant P-Sub DNW UV 1.8 N-well formation mask2 Etch Implant photoresist,Si3N4 remove 1.10 P-well formation mask3 P-Sub DNW N-well P-well B+ 1.11 Vth adjust implant mask4 P-Sub DNW N-well P-well As N-well Vth implant use double implants: 1)Punch-through implant ,As+ 2)Vth implant ,As- 3) So does P-well P-Sub DNW N-well P-well 1.12 Vth adjust implant mask5 B Double implants for better device performance: 1)To prevent S/D punch-through 2) Suppress off-state leakage of FETs P-Sub DNW N-well P-well 1.13 Si3N4 deposition 1) Photoresist,Si3N4 remove 2) Si3N4 depositon etch N-well P-well DNW P-Sub P-Sub DNW N-well P-well 1.14 STI formation mask6 UV mask photoresist (posi) Si3N4 SiO2 Vth adjust Photoresist remove SiO2 deposition CMP (Chemical mechanical polish) Add photoresist (Nega) Use