an766了解和优化时钟缓冲附加抖动性能-AN766.PDFVIP

AN766 UNDERSTANDING AND O PTIMIZING C LOCK B UFFER ’S A DDITIVE J ITTER P ERFORMANCE 1. Introduction This application note details the various contributions to a clock distribution’s buffer’s additive phase noise performance and how to optimize performance without increasing costs. High speed communications requires system designers to optimize clocking performance while adhering to both performance and cost budget restraints. The optimal clock must be selected considering performance, cost, size, and output logic, to name a few; but the focus is on phase noise, for those who work in the frequency domain, or jitter which is the time domain equivalent. Often the refere nce clock needs to be distributed to a variety of logic inputs and locations on a PC board design which is accomplished by using a distribution buffer. The clock buffer now becomes part of the equation when determining the overall performance and while the clock noise is characterized as phase noise or jitter, the distribution buffer is characterized as additive phase jitter. This application note will show the dependence of additive jitter on i) input rise and fall time at a given amplitude, or slew rate ii) output format and iii) power supply voltage, and how to maximize clock buffer performance. Engineers working on clocks understand the importance of power supply decoupling and signal integrity. What may get overlooked is that the input rise and fall time has a significant impact on additive phase jitter. While on first glance this is true, what makes the statement even more accurate is to consider both the amplitude versus rise and fall time, which is expressed as Volts/ns—or slew rate. Most engineers would associate slew rate with analog components, such as an