74HCT377D,652,74HC377D,653,74HC377D,652,74HCT377PW,118,74HCT377PW,112, 规格书,Datasheet 资料.pdfVIP

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT377 Octal D-type flip-flop with data enable; positive-edge trigger Product specification December 1990 File under Integrated Circuits, IC06 芯天下--/ Philips Semiconductors Product specification Octal D-type flip-flop with data enable; 74HC/HCT377 positive-edge trigger FEATURES GENERAL DESCRIPTION • Ideal for addressable register applications The 74HC/HCT377 are high-speed Si-gate CMOS devices • Data enable for address and data synchronization and are pin compatible with low power Schottky TTL applications (LSTTL). They are specified in compliance with JEDEC standard no. 7A. • Eight positive-edge triggered D-type flip-flops • See “273” for master reset version The 74HC/HCT377 have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common • See “373” for transparent latch version clock (CP) input loads all flip-flops simultaneously when • See “374” for 3-state version the data enable (E) is LOW. The state of each D input, one • Output capability: standard set-up time before the