基于FPGA平台的电路级抗差分功耗分析研究-北京大学学报（自然科学版）.PDF

北京大学学报(自然科学版), 第 50 卷, 第 4 期, 2014 年 7 月 Acta Scientiarum Naturalium Universitatis Pekinensis, Vol. 50, No. 4 (July 2014) doi: 10.13209/j.0479-8023.2014.097 基于FPGA 平台的电路级抗差分功耗分析研究 † 黄颖 崔小欣 魏为 张潇 廖凯 廖楠 于敦山 北京大学信息科学技术学院微电子学研究院 , 北京 100871; † 通信作者 , E-mail: cuixx@pku.edu.cn 摘要 研究 DPA 攻击方法以及相应的电路级防护技术, 提出在 FPGA (现场可编程门阵列)上实现 WDDL 的 设计方法以及适用于 FPGA 的对称布线技术, 随后在 FPGA 平台上实现一个 4 位加法器并进行功耗分 析。实验结果表明, WDDL 电路的功耗波动比普通电路有较明显的下降。WDDL 结构以一定的芯片面积为 代价, 可有效降低 FPGA 功耗与数据的相关性, 具有较好的抗 DPA (差分功耗分析)攻击性能。 关键词 差分功耗分析(DPA); WDDL; 对称布线 ; FPGA 中图分类号 TN47 Research on DPA Resistant Circuit for FPGA † HUANG Ying, CUI Xiaoxin , WEI Wei, ZHANG Xiao, LIAO Kai, LIAO Nan, YU Dunshan Institute of Microelectronics, School of Electronics Engineering and Computer Science, Peking University, Beijing 100871; † Corresponding author, E-mail: cuixx@pku.edu.cn Abstract The authors studied the DPA attack method and circuit level protection technology, and introduced a security circuit WDDL on FPGA and a new symmetrical routing technology. A 4-bit WDDL adder on FPGA (field programmable gate array) platform was implemented and the power consumption of the circuit was analyzed. The results show that power consumption of WDDL decreases obviously than that of the traditional circuit and WDDL circuit can reduce the correlation of power consumption and data effectively. WDDL is proved to have better anti DPA (differential power analysis) attack ability at the cost of chip size. Key words DPA; WDDL; symmetrical routing; FPGA 近年来, 互联网的高速发展彻底改变了人们的 分功耗分析(differential power analysi