第10节 Verilog硬件描述语言实例.pptVIP

* * * * * * * * * * * * * * * * * * * S0: begin op =0; if (din==0) next_state = S0; else next_state = S1; end //第二个always进程——组合逻辑电路 always@(current_state or din) begin case( current_state ) S1: begin op =1; if (din==1) next_state = S1; else next_state = S2; end S2: begin op =0; if (din==1) next_state = S2; else next_state = S3; end S3: begin op =0; if (din==0) next_state = S3; else next_state = S0; end default: //case缺省项，防止产生锁存器 begin op =0; next_state = S0; end endcase end