3DNOC低功耗编码技术精要.docVIP

摘要 随着集成电路工艺尺寸的不断减小集成的核数量逐渐增多，传统的以总线为通信架构的SoC遇到了性能瓶颈。为了解决该问题就必须寻求新的技术，进而出现了三维集成电路和片上网络(NoC)技术。三维集成电路提供了一种新的提高IC集成度的途径，其中通孔硅（TSV）技术被认为是三维集成电路中非常重要的互连技术。而NoC使得IC设计中越来越多的处理核或IP之间能更有效地通信。研究人员将这两个研究热点结合在一起，进而提出了3D NoC的概念。 功耗依旧是3D NoC中需要着重考虑的问题，常采用低功耗处理的技术手段有数据编码技术和低摆幅电路技术。本文将数据编码技术应用于3D NoC互连结构当中，以改善TSV互连线功耗、延时和可靠性问题。其中数据编码电路采用EFPC-BI编码方法，将32bit数据流预先通过串行编码转换成8bit，随后经过FPC和BI编码最后得到数据长度为14bit。EFPC-BI编码电路用verilog语言实现，经验证可以使互连功耗下降18%-60%左右。 关键词：3D NoC TSV 互连 低功耗 编码 Abstract With the rapid development of process technology and the increasing number of IP cores in a single chip, the traditional SoC architecture based on bus has appeared bottlenecks.In order to solve this problem,Three-dimensional IC is a way to improve density of transistors on a chip and TSV is considered as one of key technologies in this problem.NoC can supply a more effective way to transfer data than bus structures in systems with more and more IPs.These two innovations were founded and then connected spontaneously, coming up with the concept of 3D NoC. As the power is one of the important considerations in 3D NoC,there are two effective ways to solve above problems: data coding technology and low-swing technology.In this paper, a method of data Coding is proposed, which is applied to the Interconnect of 3D NoC. The new encoding technique is called EFPC-BI which is based on the FPC-BI.The method of EFPC-BI is realized by Verilog language, and simulations show that this coding method can reduces the energy dissipation by up to 18%-60%. Keywords: 3D NoC TSV Interconnect Low Power Coding 目 录 第一章 绪论 1 1.1 研究背景 1 1.1.1集成电路三维化 1 1.1.2 3D NoC简介以及其中功耗的影响 2 1.1.3 基于硅通孔的三维集成技术 2 1.2 论文主要内容和章节安排 4 第二章 TSV的结构及互连 7 2.1 TSV的结构 7 2.2 TSV电学参数的提取及计算 9 2.2.1 TSV的电阻和电感 9 2.2.2 TSV的MOS寄生电容 10 2.2.3 硅衬底的电容和电导 11 2.2.4 TSV电阻和电容的计算 12 2.3 TSV互连 12 第三章 数据编码技术 15 3.1 数据编码技术简介 15 3.2 数据编码技术 15 3.2.1低功耗编码 15 3.2.2串扰抑制编码 19 3.2.3检错/纠错编码 21 3.3 统一编码方法 23 第四章 3D NoC的低功耗编码处理 25 4.1串行EFPC-BI编码方案 25 4.1.1 串行低功耗串扰抑制编码原理和整体方案 25