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基于FPGA数字系统设计实验3控制液晶显示屏显示字符OK
Jian程序
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd is
port(
clk, reset : in bit;
SF_D : out bit_vector(3 downto 0);
LCD_E, LCD_RS, LCD_RW, SF_CE0 : out bit;
LED : out bit_vector(7 downto 0) );
end lcd;
architecture behavior of lcd is
type tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold, fortyus, done);
signal tx_state : tx_sequence := done;
signal tx_byte : bit_vector(7 downto 0);
signal tx_init : bit := 0;
type init_sequence is (idle, fifteenms, one, two, three, four, five, six, seven, eight, done);
signal init_state : init_sequence := idle;
signal init_init, init_done : bit := 0;
signal i : integer range 0 to 750000 := 0;
signal i2 : integer range 0 to 2000 := 0;
signal i3 : integer range 0 to 82000 := 0;
signal SF_D0, SF_D1 : bit_vector(3 downto 0);
signal LCD_E0, LCD_E1 : bit;
signal mux : bit;
type display_state is (init, function_set, entry_set, set_display, clr_display, pause, set_addr, char_f, char_p, char_g,
char_a, done);
signal cur_state : display_state := init;
begin
LED = tx_byte; --for diagnostic purposes
SF_CE0 = 1; --disable intel strataflash
LCD_RW = 0; --write only
--The following with statements simplify the process of adding and removing states.
--when to transmit a command/data and when not to
with cur_state select
tx_init = 0 when init | pause | done,
1 when others;
--control the bus
with cur_state select
mux = 1 when init,
0 when others;
--control the initialization sequence
with cur_state select
init_init = 1 when init,
0 when others;--register select
with cur_state select
LCD_RS = 0 when function_set|entry_set|set_display|clr_display|set_addr,
1 when others;
--what byte to transmit to lcd
--refer to datasheet for an explanation of these values
with cur_state select
tx_byte =when function_
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