Computer-AidedVLSISystemDesign分析.docVIP

Computer-Aided VLSI System Design Dft Compiler Lab 1: Insert Scan Chain Objectives: In this lab, you will learn: 1. How to insert scan chain into a synthesized gate level design Copy Files from CSDTA Directory 1. copy all the files into your work directory, cp –R ~cvsd/06F/DftCompiler/Lab1 . 2. check if you have these files filename Description Lab1_alu_synth.v synthesized gate level Verilog code for the simple ALU (no scan chain yet) DftCompilerLab1.script scripts to run DftCompiler .synopsys_dc.setup Synopsys Dft Compiler setup file (same format as Design Compiler). defin