ATCA的双重star_20090522_ritht [ 001 ].pptVIP

* * * * * * * * Base IF GbE Switch Failover interface example (AFOI) Proprietary interface checkpointing over base fabric redundant hub blades for high availability update channel as proprietary link between two blades GbE CPU Update channel Base IF FPGA Bus IF GbE CPU Update channel Base IF FPGA Bus IF Base IF GbE Switch Hub blade redundant vs. non-redundant ATCA is used in two scenarios: redundancy at board level = telecom style = 1+1 redundancy no redundancy / redundancy at box level = networking/enterprise style in telecom environments (e.g. NSN AB3), update channel will be used for failover in enterprise environments (e.g. Nortel, Comverse), update channel may be used for PCIe Advantech should support both modes as a software coinfigurable (over BMC/IPMI) option Update channelimplementation guidelines Update channel mux need a 5 channel 2-to-1 mux multiplexer is controlled by BMC to support e-keying and selection of PCIe or Update channel mode IO pin can be implemented on BMC or FPGA Mux Implementation: mux data rate is determined by PCIe speed. Failover interface is lower speed use a PCIe gen2 (5Gbps) 4 channel 2-to-1 mux for ports 0..3 used for PCIe lanes 0..3 use a lower speed single channel 2-to-1 mux for port 4 used for PCIe reference clock CPU failover PCIe FPGA BMC M U X Upd. Ch. Control Update channel port map use case Update channel 0 1 2 3 4 PCIe extension ? PCIe lane 0 PCIe lane 1 PCIe lane 2 PCIe lane 3 PCIe REF_CLK, PCIe_RST Failover AFOI failover ? AFOI-C Alarm channel AFOI-C message channel ? ? Gbe based failover Serdes #1 ? ? Serdes # 2 ? Clock generator failover ? ? ? ? MCG_REF_IN,MCG_REF_OUT PCIe guidelines Blades acting as root complex: x86 blades NPU blades Blades acting as endpoint: AMC Carriers PCIe ports shall be AC coupled at the receiver board side of update channel mux, not backplane side PCIe reference clock shall be terminated inside endpoint direct drive from PCIe clock gen