7-存储器-1(SDRAM-ROM,2节).PPT

地址同时送各个存储体，无地址锁存 数据寄存器的作用：buffer！ * * 地址依次送各个存储体，需要各个锁存 注意：数据寄存器宽度应为单体字宽，而不是图示这么宽。 DRAM存储器需要逐行定时刷新，而且,DRAM芯片的读出是一种破坏性读出，因此在读取之后要立即按读出信息予以充电再生。 这样，若CPU先后两次读取的存储字使用同一RAS选通信号的话，CPU在接收到第一个存储字之后必须插入等待状态，直至前一存储字再生完毕才开始第二个存储字的读取。由于采用m=2的交叉存取度的成块传送，两个连续地址字的读取之间不必插入等待状态（零等待存取）。 Memory Systems - Cache, DRAM, Disk(书2008).pdf Inline的意思不知道，有outline，好像用于小型系统，如笔记本（见此书10.3.4 Small Outline DIMM (SO-DIMM)） 固态技术协会JEDEC是微电子产业的领导标准机构 The busses in a JEDEC-style organization are classified by their function and organization into data, address, control, and chip-select busses. The data bus that transmits data to and from the DRAMs is relatively wide. It is often 64 bits wide, and it can be much wider in high-performance systems. A dedicated address bus carries row and column addresses to the DRAMs, and its width grows with the physical storage on a DRAM device (typical widths today are about 15 bits). A control bus is composed of the row and column strobes, output enable, clock, clock enable, and other related signals. These signals are similar to the address-bus signals in that they all connect from the memory controller to every DRAM in the system. Finally, there is a chip-select network that connects from the memory controller to every DRAM in a rank (a separately addressable set of DRAMs). For example, a memory module can contain two ranks of DRAM devices; for every DIMM in the system, there can be two separate chip-select networks, and thus, the size of the chip-select “bus” scales with the maximum amount of physical memory in the system. This last bus, the chip-select bus, is essential in a JEDEC-style memory system, as it enables the intended recipient of a memory request. A value is asserted on the chip-select bus at the time of a request (e.g., read or write). The chip-select bus contains a separate wire for every rank of DRAM in the system. The chip-select signal passes over a wire unique to each small set of DRAMs and enables or disables the DRAMs in that rank so that