VHDL键盘去动计数器.docVIP

实验三 键盘扫描显示实验 实验目的实验实验数据library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity scanf is port( clk : in std_logic;-------------扫描时钟信号 start : in std_logic;-------------开始信号，高电平有效 kbcol : in std_logic_vector(3 downto 0);--------------行扫描信号 kbrow : out std_logic_vector(3 downto 0);-------------列扫描信号 seg7_out : out std_logic_vector(6 downto 0);-------------七段显示控制信号(abcdefg) scan : out std_logic_vector(2 downto 0));-------------数码管地址选择控制信号 end scanf; architecture one of scanf is signal count : std_logic_vector(1 downto 0); signal sta : std_logic_vector(1 downto 0); signal seg7 : std_logic_vector(6 downto 0); signal dat : std_logic_vector(4 downto 0); signal fn : std_logic;------------------按键标志位，判断是否有键被按下 begin scan=000;---------------只使用一个数码管显示 ---------------------循环扫描计数器 process(clk) begin if clkevent and clk=1 then count=count+1; end if; end process; ---------------------循环列扫描 process(clk) begin if clkevent and clk=1 then case count is when 00=kbrow=0001;sta=00; when 01=kbrow=0010;sta=01; when 10=kbrow=0100;sta=10; when 11=kbrow=1000;sta=11; when others=kbrow=1111; end case; end if; end process; ---------------------行扫描译码 process(clk,start) begin if start=0 then seg7=0000000; elsif clkevent and clk=1 then case sta is when 00= case kbcol is when 0001=seg7=1111001;dat=00011;-----3 when 0010=seg7=1101101;dat=00010;-----2 when 0100=seg7=0110000;dat=00001;-----1 when 1000=seg7=1111110;dat=00000;-----0 when others=seg7=0000000;dat=11111; end case; when 01= case kbcol is when 0001=seg7=1110000;dat=00111;-----7 when 0010=seg7=