低噪声放大器简介2015.pptVIP

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * Folded cascode Low supply voltage Ld reduces or eliminates Effect of Cgd1 Good fT Design Procedure for Inductive Source Degenerated LNA Noise factor equations: Targeted Specifications Frequency 2.4 GHz ISM Band Noise Figure 1.6 dB IIP3 -8 dBm Voltage gain 20 dB Power 10mA from 1.8V Step 1: Know your process A 0.18um CMOS Process Process related tox = 4.1e-9 mm e = 3.9*(8.85e-12) F/m m = 3.274e-2 m^2/V.s Vth = 0.52 V Noise related a = gm/gdo d/g ~ 2 g ~ 3 c = -j0.55 Step 2: Obtain design guide plots Insights: gdo increases all the way with current density Iden gm saturates when Iden larger than 120mA/mm Velocity saturation, mobility degradation ---- short channel effects Low gm/current efficiency High linearity a deviates from long channel value (1) with large Iden Obtain design guide plots Insights: fT increases with Vod when Vod is small and saturates after Vod 0.3V --- short channel effects Cgs/W increases slowly after Vod 0.2V fT begins to degrade when Vod 0.8V gm saturates Cgs increases Should keep Vod ~0.2 to 0.4 V Obtain design guide plots 3-D plot for visual inspection 2-D plots for design reference knf vs input Q and current density Design trade-offs For fixed Iden, increasing Q will reduce the size of transistor thus reduce total power ---- noise figure will become larger For fixed Q, reducing Iden will reduce power, but will increase noise factor For large Iden, there is an optimal Q for minimum noise factor, but power may be too high Obtain design guide plots Linearity plots :IIP3 vs. gate overdrive and transistor size Insights: MOS transistor IIP3 only, when embedded into actual circuit: Input Q will degrade IIP3 Non-linear memory effect will degrade IIP3 Output non-linearity will degrade IIP3 IIP3 is a very weak function of device size Generally, large overdrive