StratixV器件中的收发器配置方案.PDFVIP

Stratix V器件中的收发器配置 4 2013.05.06 SV52005 订阅 反馈 Stratix®V器件含有一个专用的收发器物理编码子层(PCS)和物理介质附加子层(PMA) 电路。 要实现一个协议，请使用表4-1 中所列出的PHY IP 。 Stratix V器件支持以下通信协议： • 10GBASE-R和10GBASE-KR • Interlaken • PCI Express® (PCIe®)—Gen1、Gen2和Gen3 • CPRI和OBSAI—确定性延迟(Deterministic Latency)协议 • XAUI 通过使能下面的PHY IP可支持其他的通信协议或者用户定义的协议： • Native PHY IP使用standard PCS和10G PCS硬件选项，包括在不同的PCS选项之间的可重置性 • Custom PHY IP在定制的数据通路中使用standard PCS • Low Latency PHY IP在低延迟数据通路配置中使用standard或者10G PCS 相关链接 • Stratix V器件手册: 已知问题 列出了对Stratix V器件手册章节所规则的更新。 • Upcoming Stratix V Device Features • Altera收发器PHY IP Core用户指南 © 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at ISO /common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with 9001:2008 Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes Registered no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 101 Innovation Drive, San Jose, CA 95134