采用状态机设计方法设计的序列检测.pptxVIP

采用状态机方法设计的1101序列检测;本设计是用Verilog HDL语言编写的，采用状态机方法设计的1101序列检测。 有复位、时钟、信号输入按键，在BASYS 2开发板上分别对应G12/C11/P11按键，LED等M5，为信号输出。;代码如下： module jian_ce_1101(clk,rest,D,Q,present_state ); input clk;//时钟 input rest;//复位 input D;//输入 output Q;//输出 output reg [4:0]present_state;//状态寄存器，可以不用作为输出 //用独热编码编写的5个状态 parameter S0=5b00001,S1=5b00010,S2=5b00100,S3=5b01000,S4=5b10000; always@(posedge clk or posedge rest)//状态转换 begin if(rest==1b1) present_state=S0; else case(present_state) S0: if(D==1b1) present_state=S1; else present_state=S0; S1: if(D==1b1) present_state=S2; else present_state=S0;; S2: if(D==1b0) present_state=S3; else present_state=S2; S3: if(D==1b1) present_state=S4; else present_state=S0; S4: if(D==1b1) present_state=S2; else present_state=S0; default:present_state=S0; endcase end //输出与状态寄存器的逻辑关系 assign Q=present_state[4]~present_state[3]~present_state[2]~present_state[1]~present_state[0]; endmodule;在BASYS 2开发板上的管脚配置如下，最后一句不能缺： NET clk LOC = C11; NET rest LOC = G12; NET D LOC = P11; NET Q LOC = M5; NET present_state[4] LOC = G1; NET present_state[3] LOC = P4; NET present_state[2] LOC = N4; NET present_state[1] LOC = N5; NET present_state[0] LOC = P6; NET clk CLOCK_DEDICATED_ROUTE = FALSE;;仿真测试代码如下： module test; reg clk; reg rest; reg D; wire Q; wire [4:0] present_state; jian_ce_1101 uut ( .clk(clk), .rest(rest), .D(D), .Q(Q), .present_state(present_state) ); initial begin clk = 0; rest = 1; D = 0; #5; rest=0; end; always #10 clk=~clk; initial begin #8;D=1; #20;D=1; #20;D=0; #20;D=1; #20;D=1; #20;D=1; #20;D=0; #20;D=0; #20;D=1; #20;D=0; #20;D=0; end endmodule