很有用的Quartus模板.docxVIP

很有用的Quartus?II里面的verilog文件模板?单口RAM// Quartus II Verilog Template// Single port RAM with single read/write address?modulesingle_port_ram(???????input [(DATA_WIDTH-1):0] data,???????input [(ADDR_WIDTH-1):0] addr,???????input we, clk,???????outputreg [(DATA_WIDTH-1):0] q);????????parameter DATA_WIDTH = 8;???????parameter ADDR_WIDTH = 6;????????// Declare the RAM variable???????reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];????????always @ (posedgeclk)???????begin??????????????// Write??????????????if (we)?????????????????????ram[addr] = data;???????????????// Read returns NEW data at addr if we ==