数电课件第七章.pptx

Digital Fundamentals-7 Latches, Flip-Flops, and Timers Chapter Seven: Latches, Flip-Flops, and Timers 7-1 Latches 7-2 Edge-Triggered Flip-Flops 7-3 Flip-Flop Operating Characteristics 7-4 Flip-Flop Applications 7-5 One-Shots 7-6 The 555 Timer New and key terms Latch[锁存器]-A bistable digital circuit used for storing a bit. Bistable[双稳]-Having two stable states. Flip-Flops and latches are bistable multivibrators. SET[置1]-The state of a flip-flop or latch when the output is 1; the action of producing a SET state. RESET[置0]-The state of a flip-flop or latch when the output is 0; the action of producing a RESET state. Edge-triggered flip-flop[边沿触发的触发器]-A type of flip-flop in which the data are entered and appear on the output on the same clock edge. Synchronous[同步]-Having a fixed time relationship. D flip-flop[D触发器]-A type of bistable multivibrator in which the output assumes the state of the D input on the triggering edge of a clock pulse. Digital Fundamentals-7 Latches, Flip-Flops, and Timers New and key terms J-K flip-flop[J-K触发器]-A type of flip-flop that can operate in the SET, RESET, no-change, and toggle modes. Toggle[切换]-The action of a flip-flop when it changes state on each clock pulse. Preset[预置数]-An asynchronous input used to set a flip-flop(make the Q output 1). Clear[清零]-An asynchronous input used to reset a flip-flop (make the Q output 0) Set-up time[建立时间]-The time interval required for the control levels to be on the inputs to a digital circuit, such as a flip-flop, prior to the triggering edge of a clock pulse. Digital Fundamentals-7 Latches, Flip-Flops, and Timers New and key terms Hold time[保持时间]-The time interval required for the control levels to remain on the inputs to a flip-flop after the triggering edge of the clock in order to reliably activate the device. Power dissipaton[功率损耗]-The amount of power required by a circuit. One-shot[单稳]-A monostable multivibrator. Monostable[单稳]-Having only one stable state. A monostable multivibrator, commonly cal