可编程ASCII 第二章课件.pptx

1;Ch2 RTL Design with Verilog;Register Transfer Level Design;Digit systems:Datapath Controller;Datapath Controller ;Data-dominated systems;Control-dominated Data-dominated systems ;RTL Design;RTL Design;Control/Data Partitioning;Control/Data Partitioning;Data Part;Data Part;;Data Part;Control Part;The controller is the portion that governs the flow of the input signals through the various components comprising the datapath.;;Elements of Verilog;Elements of Verilog;Hardware Modules;;Hardware Modules;Primitive Instantiations;Primitive or Atomic action;Verilog Primitives;Verilog primitives for modelingcombinational logic gates;Primitive Instantiations;Primitive Instantiations;Assign Statements;;Condition Expression;;Procedural Blocks;Procedural Blocks;Module Instantiations;Module Instantiations;Module Instantiations;Component Description in Verilog;Data Components;Data Components;Multiplexer;Multiplexer;Flip-Flop;;Counter;Counter;Full-Adder;Half adder:(a) truth table,(b) block diagram symbol,and(c) schematic.;Full adder:(a) truth table,(b) block diagram symbol,and (c) schematic for a fulladder;Full-Adder;Full and half adders;A full adder by combining two half adders;Shift-Register;The shift register;Shift-Register;Shift-Register (Continued);ALU;;ALU (Continued);Interconnections;Interconnections;Interconnections;Interconnections;verilog 模块的例化(引用) 1）引用时，严格按照模块定义的端口顺序来连接，不用标明原模块定义时规定的端口名。 Design u_1(u_1的端口1，u_1的端口2，u_1的端口3， u_1的端口……)； //和Design对应 2）引用时用 “ . ” 符号，标明原模块定义时规定的端口名： Design u_2(??.(端口1(u_2的端口1), ?.(端口2(u_2的端口2), ?.(端口3(u_3的端口3), ……? ?);??//推荐这种引用法;传递的参数是子模块中定义的parameter 传递的方法：1、module_name #( parameter1, parameter2) inst_name( port_map);2、module_name #( .parameter_name(para_value), .parameter_name(para_value)) inst_name (port map);;Controllers;Controllers;Controllers;Controllers;Synchronizer;Synchronizer;Synchronizer;Sequence Detector;Finite State Machines;Mealy Moore State Machine; 常用的编码方式： 曼彻斯特码（Manchester），也称相位编码 原理：每一位中间都有一个跳变，从低