如何进行设计优化(一个IC设计优化的实例).pdfVIP

A Comparison of Hierarchical Compile Strategies Steve Golson Trilobyte Systems 33 Sunset Road Carlisle MA 01741 Phone: +1.978.369.9669 Fax: +1.978.371.9964 Email: sgolson@ ABSTRACT A wealth of new hierarchical compile strategies have become available in the last few years. This paper will compare area, speed, and compile time for several large designs using a variety of hierarchical compile strategies: top-down compile, top-down simple compile, bottom-up with default constraints, bottom-up with hand-crafted constraints, and ACS (Automated Chip Synthesis). 1.0 Introduction Synthesis of large hierarchical designs has traditionally been done in a bottom-up manner: leaf modules are compiled, and then glued together with no further compilation. Top-down compilation was generally not an option due to capacity restrictions in Design Compiler. However the capabilities of Design Compiler have grown dramatically in recent years, and several new synthesis techniques have become available. This paper compares these new techniques with the old traditional compile strategies. Some1 might argue that this doesn’t matter because soon we will all be using Physical Compiler. I say not so fast, because: • the features of Physical Compiler might not be needed for your (relatively) small design or for your (comparatively) slow technology • Physical Compiler might not be supported by your silicon vendor’s flow • even if it is supported by your vendor, you might be required to provide a traditional netlist to the vendor who runs Physical Compiler themselves in gates-to-gates mode2 • Physical Compiler is really o