基于FPGA的10 Gbit／s伪随机序列测试装置.pdfVIP

Journal of Southeast University(English Edition) Vo1．23，No．4，PP．516—519 Dec．2007 ISSN 1003—7985 10 Gbit／s PRBS tester implemented in FPGA Miao Peng Wang Zhigong f Institute of RF一OE—ICs，Southeast University，Nanjing 210096，China) Abstract：The design of an f甲GA(field programmable gate array)based programmable S0NET(synchronous optical network)OC．192 10 Gbit／s PRBS(pseudo—random binary sequence)generator and a bit interleaved pol tv 8(BIP．8)error detector is presented．Implemented in a parallel feedback configuration，this tester fleatures PRBS genermion of sequences with bit lengths of 2 一1，2…一1，2”一1，2 一1and 2 一1 for up to 10 Gbit／s applications with a 10 Gbit／s optical transceiver，via the SFI-4(OC一192 serdes—framer interface)．In the OC一192 flame alignment circuit，a dichotomy search algorithm logic which performs the functions of word alignment and STM—64／0C192 de—fram e speeds up the frame sync logic and reduces circuit complexity greatly． The system can be used as a low cost tester to evaluate the perform ance of OC一192 devices and components． taking the replacement of precious commercial PRBS testers． Key words：bit interleaved polarity 8 (BIP一8)；synchronous digital hierarchy (SDH)；framer；field programmable gate array(FPGA)；pseudo—random binary sequence(PRBS) Reliable testing at 10 Gbit／s has become a major aligned to the OC一192 fram e structure，the BIP一8 calcu— issue in the development of high speed optical fiber lation unit counts bit polarity errors communication systems f e．g．，SONET 0C．192)and PRBS generatorl 64 入 related high—speed components．PRBS f pseudo random oc一192 fmIn目r 4CH