EDA技术与verilog设计第6章作业题部分答案.ppt

6-11;6-11仿真波形;6-12;6-12;6-12;6-13;6-13;6-13;6-13;6-14;6-14;6-15;6-15;6-15;6-16;6-16;6-16;四级流水线实现的32位加法器;四级流水线实现的32位加法器;四级流水线实现的32位加法器;四级流水线实现的32位加法器;四级流水线实现的32位加法器;8x8乘法器实现;8x8乘法器实现;7-5 编写4位并-串转换电路;模为9的占空比50%的奇数分频;always @(negedge CLK) begin if(!RESET) begin COUT2=0; n=0; end;模为9.3的小数分频;模为9.3的小数分频;习题10-3 “1001”二进制序列检测器;module wytest(reset,clk,in,out); input reset,clk,in; output out; reg out; reg[1:0] state,next_state; parameter s0=2d0,s1=2d1,s2=2d2,s3=2d3; always@(posedge clk) begin if(!reset) state=s0; else state=next_state; end always@(state or in) case(state) s0:if(in==1) next_state=s1; else next_state=s0; s1:if(in==0) next_state=s2; else next_state=s1; s2:if(in==0) next_state=s3; else next_state=s1; s3:if(in==1) next_state=s1; else next_state=s0; default:next_state=s0; endcase