数字逻辑chapter5_b概要1.ppt

5.3.8 The Time Dimension VHDL allows you to specify a time delay using the keyword After in any signal-assignment statement (sequentical, concurrent, conditional or selected). Example of the use of after: Z = ‘1’ after 4 ns when X=‘1’ and Y=‘0’ else ‘0’ after 3 ns; To model an inhibit gate that has 4ns of delay on a 0-to-1 output transition and only 3 ns on a 1-to-0 output transition . VHDL wait statement The sequential statement wait suspends a process for a specified time period. Example: to generate input waveform architecture InhibitTB_arch of InhibitTestBench is component Inhibit port (X,Y: in BIT; Z: out BIT); end component; signal XT,YT,ZT: BIT; begin U1: Inhibit port map (XT,YT,ZT) process begin XT = 0; YT = ‘0; wait for 10 ns; XT = 0; YT = ‘1; wait for 10 ns; XT = ‘1; YT = ‘0; wait for 10 ns; XT = ‘1; YT = ‘1; wait ; -- this suspends the process indefinitely end process; end InhibitTB_arch; 5.3.9 Simulation We can use simulator to observe VHDL program’s operation. With a time-based event list and a signal-sensitivity matrix based on the signal-sensitivity lists of all the processes, the simulator can finish the simulation. Simulator operation begins at simulation time of zero. Then it begins the execution of all the processes and concurrent statements in the design. Simulation cycle: at simulation time zero, one of the processes is executed. When it is completed, another one is selected for execution, and so on, until all of the processes have been executed. 5.3.10 Test Benches Test Bench specifies a sequence of inputs to be applied by the simulator to an HDL-based design ,such as a VHDL entity. The basic parts of a VHDL test-bench program: There is an entity declaration , it has no inputs or outputs. Architecture definition makes a component declaration for the UUT, the UUT is instantiated using local signals for its inputs and outputs. A process with no sensitivity list starts at simulation tim