全包覆式电晶体之最佳化设计-国家奈米元件实验室.PDF

NANO COMMUNICATION 21 No. 1 9 Optimal Design of Gate-All-Around SOI MOSFETs 1 1 2 1 2 22 Bulk Abstract A comprehensive yet simple design methodology of si licon nanowire MOSFETs is presented. An analytical gate capacitance model for sub-22 nm gate length is also proposed to gain insight into design optimization with quantum connement included. In contrast to conventional bulk device design, this work shows that the wire diameter does not necessarily follow the common stringent scaling rule. An optimal device design window does exist while a moderate wire diameter dimension is suggested without the need of extremely scaled dimension. The nanowire diameter designed at two thirds of gate length minus three times gate oxide thickness is shown to achieve good control of short-channel eects for silicon nanowire MOSFETs. Keywords Design Window Subthreshold Swing Intrinsic Delay Gate Capacitance nanowire 10 (MOSFET) (Integrated Circuit, IC) (Scaling) (Channel Length) 1