Verilog比较好一篇教程.pptVIP

Verilog;Verilog Application Introduction to Cadence Simulators Sample Design Lexical Conventions in Verilog Verilog Data Type and Logic System Structural Modeling Modeling Delay Using Compiler Controls Verilog Operators Behavioral Modeling Support for Verification Introduction to Using a Verilog Test Bench Modeling Memories High Level Constructs in Verilog User Defined Primitives Annotating SDF Timing;IEEE 1364-1995, IEEE 1364-2001 Behavioral: 無法看出電路特性 RTL:可以看出電路特性 (logic synthesis) Structural: bulit-in primitives,UDPs RTL and structural 可混合描述 Behavioral 和 RTL的區分要靠經驗;Compilation(1) Initialization(2) Simulation(3) Verilog-XL simulator:Interpretive 不會有暫存檔(1)(2)(3)一次完成 NC Verilog simulator:compiled simulation ncviog(1) ncelab(2) ncsim(3) 當project很大時,只針對要修改部分重新compile即可 VHDL and Verilog可以作整合 Simulation algorithms Time-based(SPICE) Event-based(Verilog-XL and NC Verilog) Cycle-based(依照clock,更大的time-based) ;verilog mux.v testbench.v verilog –f run.f The waveform display tool---signalscan Read data from database SHM database(非IEEE standard,only Cadence) VCD(Value Change Dump) database(IEEE standard) ;Testbench----behavioral Procedural block Initial always ;Waveform database(SHM and VCD);`include global.v verilog mux.v global.v timescale 1ns/100 ps Lumped delay nor n1(net1,a,b); or #3 o1(out,c,net1); Distributed delay nor #2 n1(net1,a,b); or #1 o1(out,c,net1); Module path delay Specify (A=O)=2; (A=O)=3; (A=O)=1; //state dependent path delay if(a) (b=x)=(5:6:7); //state dependent delay 無else的語法 Endspecify specify block ;Selecting simulation delay mode;Parallel connection (a,b = q,qb)=15; (a=q)=15; (b=qb)=15; Full connection (a,b * q,qb)=15; (a=q)=15; (b=q)=15; (a=qb)=15; (b=qb)=15; ;Timing checks in Verilog(物理特性) Setup,hold,pulse width,clock period,skew,recovery SDF(Standard Delay Format) tool-independent text format for representing timing data Allows timing data to be shared between tools Interconnect delay 因製程技,使inter