用Verilog HDL编写的四路抢答器概要1.pptxVIP

四路抢答器设计;抢答器为四路，20秒倒计时，抢到后显示锁定，计时停止，若提前抢答会在另外数码管显示抢答号码。 在BASYS 2 开发板上可以实现;module qiang_da_qi(a_to_g,A_TO_D,clk,qiang_da,button,xuan ); output wire [6:0]a_to_g; output wire [3:0]A_TO_D; input wire clk;//50MHz时钟 wire [3:0]qian; wire [3:0]bai; wire [2:0]shi; wire [2:0]ge; wire cp;//1s时钟 input wire [3:0]qiang_da; input button; wire suo_1; wire [2:0]bian_ma_cun; wire fankui; output wire xuan; shumaguan shumaguan0(a_to_g,A_TO_D,clk,qian,bai,shi,ge); cp_1s cp_1s0(clk,cp); xuan_shou xuan_shou0(qiang_da,button,suo_1,bian_ma_cun,fankui); wei_xuan wei_xuan0(bian_ma_cun,xuan,shi,ge); fuwei_kongzhi fuwe