《数字集成电路设计》[课件-第六章].PPTVIP

EE141 * EE141 * EE141 * EE141 * EE141 * For class lecture. Red sizing assuming Rp = Rn Follow short path first; note PMOS for C and B 4 rather than 3 – average in pull-up chain of three – (4+4+2)/3 = 3 Also note structure of pull-up and pull-down to minimize diffusion cap at output (e.g., single PMOS drain connected to output) Green for symmetric response and for performance (where Rn = 3 Rp) Sizing rules of thumb PMOS = 3 * NMOS 1 in series = 1 2 in series = 2 3 in series = 3 etc. EE141 * While output capacitance makes full swing transition (from VDD to 0), internal nodes only transition from VDD-VTn to GND C1, C2, C3 on the order of 0.85 fF for W/L of 0.5/0.25 NMOS and 0.375/0.25 PMOS CL of 3.2 fF with no output load (all diffusion capacitance – intrinsic capacitance of the gate itself). To give a 80.3 psec tpHL (simulated as 86 psec) EE141 * Fixed fan-out (NMOS 0.5 micrcon, PMOS 1.5 micron) tpLH increases linearly due to the linearly increasing value of the diffusion capacitance tpHL increase quadratically due to the simultaneous incrase in pull-down resistance and internal capacitance EE141 * slope is a function of the driving strength EE141 * a1 term is for parallel chain, a2 term is for serial chain, a3 is fan-out EE141 * M1 have to carry the discharge current from M2, M3, … MN and CL so make it the largest MN only has to discharge the current from MN (no internal capacitances) EE141 * For lecture. Critical input is latest arriving signal Place latest arriving signal (critical path) closest to the output EE141 * Reduced fan-in - deeper logic depth Reduction in fan-in offsets, by far, the extra delay incurred by the NOR gate (second configuration). Only simulation will tell which of the last two configurations is faster, lower power EE141 * Reduce CL on large fan-in gates, especially for large CL, and size the inverters progressively to handle the CL more effectively EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * EE141 * E