毕业论文_基于FPGA的学校打铃器设计.doc

基于FPGA的学校打铃器的设计 作 者 姓 名 专 业 电子信息工程 指导教师姓名 专业技术职务 目 录 1 第一章 绪论 3 1.1 选题目的 3 1.2 课题研究内容 4 1.2.1 FPGA的发展历程 4 1.2.2 FPGA的优点 4 1.3 器件及工具介绍 5 1.3.1 QuartusⅡ设计步骤 5 1.3.2 VHDL特点 5 系统方案设计 5 2.1 设计方案分析与选择 5 2.2 学校打铃器总体构成 6 2.3 分频模块设计 7 2.4 消抖模块设计 8 2.5 时钟模块设计 10 验结果分析 27 3.1 测试过程 27 3.2 结果分析 29 31 附 录 32 致 谢 41 摘 要 打铃器为学校上下课时间的准确控制提供了很大的便利，并且在工厂、办公室等场合也起到了提醒人们时间的作用，因此打铃器的设计有一定的实用意义。本设计的学校打铃器采用基于现场可编程门阵列（FPGA）的方法，底层模块采用硬件描述语言（HDL）设计，不仅能对时、分、秒正常计时和显示，而且还可进行闹铃时间的设定，上下课时间报警，报警时间可在1至15秒自由设定。系统主芯片采用美国Altera公司的EP3C40F484I7器件，由时钟模块、控制模块、闹钟模块、定时模块、数据译码模块、显示以及报时等模块组成，由按键进行时钟的校时、清零、启停等。本文在介绍FPGA器件的基础上，着重阐述了如何使用FPGA器件进行系统的开发，以及如何实现学校打铃系统通过及，打铃器正常计时、定时报警、报警时长设定等功能，可为日常作息提供准确、便捷的提醒。关键词：打铃器 现场可编程门阵列 硬件描述语言 ABSTRACT School Bell provides great convenience for people to control the accurate bell-time in school, and also plays an important role in the work and life in factories, offices, and many other occasions. So it is of great practical significance for us. This design is based on FPGA and the underlying module is designed by HDL. Not only can it display the right time in hour, minute and second, but the alarming time can also be setted from 1s to 15s, which rings on class time. We choose EP3C40F484I7(Altera Corp.,the USA) as the system main chip. This system is made of five modules,including the clock module, control module, alarm clock, time decoding module, display module, data and time module,etc. You can press the keys to correct or clean the time, and start or stop the clock. Based on describing devices of FPGA,this article focuses on the development method and the way to implement a school bell system.Through simulation and practical test, this system has the function of normal timing, alarming, alarming-time setting, which can provide convenient and accurate remind of daily routine.It is proved that the operation of this system is stable, and the design method is possible. Key words：alarm clock; Fi