低功耗CMOS集成运算放大器的研究与设计.PDF

37 3 Vol37, No. 3 2007 6 Micr oelectronics Jun2007 CMOS 易清明, 张 静, 石 敏 ( , 510632) : 基于0. 35 m N 阱硅栅CMOS 标准工艺, 设计了一个工作电压为 2. 5 V 的CMOS 两 级全差分 算放大器通过采用密勒电容和调零电阻串联的补偿电路, 有效地改善了电路的频率 响应特性, 提高了转换速度,使该两级 算放大器在获得较大输入共模范围和输出摆幅的同时, 还 获得了较高的增益及相位裕度, 满足便携式电子产品的低功耗高性能要求Cadence Spectre BSIM3V3模型仿真结果表明, 在 10 G 负载电阻和1 p 负载电容并联的条件下, 该两级 算放 大器的功耗为3 mW, 开环直流电压增益为73 dB, 单位增益带宽达到90 MHz, 相位裕度为47 : CMOS; 低功耗 算放大器; 差分对 + : T P342 . 1 : A :2007) Design of LowPower CMOS Operational Amplifi er YI Qingming, ZHANG Jing, SHI Min (Dep t. of Electronic Engineering, Jinan University, Guangzhou, Guangdong 510632, P. R. China) Abstract: A tw ostage CMOS fully differential operational amplif ier is designed based on standard 0. 35 m Si CMOS process. T he frequency response properties and the slew rat e of the amplifier are im proved by using compen sation circuit consisting of Miller capacitors and zeroing resist ors. T he tw ostage operational amplifier has compara tively large input range and output voltage sw ing, high gain and phase margin, w hich satisfies the lowpow er and highperformance demand of portable electronics. Cadence Spectre simulat ion using BSIM3V3 model indicates that, wit h 10G load resistor and 1p load capacitor connected in parallel, the opamp has an openloop gain of 73 dB, a unity gain bandw idth of 90 MHz and a phase margin of 47 w ith only 3 mW of pow er. Key words: CMOS; Lowpow er operational amplifier; Differential pair EEACC: 1220; 2570D , , 1 引 言 , ,