AD7705应用总结（AD7705 application summary）.doc

AD7705应用总结（AD7705 application summary） AD7705 application summary [rotation] : In the YW2314R12 project, AD7705 is used. The application experience of AD7705 and the main points of attention are summarized as follows. These experiences also apply to AD chips with calibration functions in AD7799, AD7706 and other AD companies. Timing key points: 1. The lost time of digital interface can be achieved by ADIN input for more than 32 (DCLK) pulse cycle of high level will reset AD7705 digital interface, reset after waiting for more than 500 us to visit the AD7705 chip, this way of reduction will not affect any internal registers of the AD7705, all the contents of the registers will be reset before, but lost all register in the digital interface state of content is uncertain, so it is strongly recommended that after reset to reset the AD7705 all internal registers, prevent errors. The RESET of the chips foot RESET will restore all the registers in the chip to the default value of the upper current. The clock input signal DCLK is a kind of schmidt departure signal, which can adapt to the slow edge of the optical coupler, and the increase of other digital input signals should not exceed 1us. 2. When the clock of AD7705 is greater than 2M, the CLK bit of the clock setting register should be set to 1, which should be 0 when it is less than 2M. The pulse width of DCLK should satisfy the minimum pulse width requirement. Read the data ADOUT during the low level after the clock DCLK drops. Set the data ADIN during the low level of the clock DCLK, and then write to 7705 on the rise of DCLK. Write data, read data to the number of clock DCLK (or written to be read the register) digit length is consistent, more or less than the number of clock DCLK (register length) will cause operation error. Between two write operation, ADIN should be better to keep in high level, because any (read or write) operation must be in written communication began to register, and write communication registe