nand_flash控制器（Nand_flash controller）.docVIP

nand_flash控制器（Nand_flash controller） / * clk is 125 ~ 250mhz operation: 0 ~ 128kb is used as eprom for mcu, space greater than 64k is functioned as a ata pio disk 1 read blk0: when a new efm _ r cmd is issued, if efm _ addr [31: 17] is 0, state machine to handle read sequence (read cmd, read data from buffer buffer is 512 bytes, so if addr [16: 9] hit bufferred (cache _ cor), get data from the buffer, otherwise from nand, then change the cache _ cor. blk0 give mcu initial 128kb code, then all other blocks will be accessed (read and write) by mcu as below (similar as ata pio operation) 2. mcu w: fff5 _ 0000, written data is cmd (data [7: 0]), cle w: fff5 _ 0.004, addr (data [7: 0]), ale w / r: fff5 _ 0.008, data (data [31: 0]), no group, no cle w: fff5 _ 0010 [3: 0] cmd pulse width r: fff5 _ 0014 status (ecc and busy) 3. program: mcu w 512b into fff5 _ 1000 ~ fff5 _ 11ff, the last write start program operation on nand port _ cor map: key factors: blk0 can min write 1k times. it contains basic code, which normally is not changed, and also include blk _ map address, this address is not changed and, until that block is written failed. by this way, the number of write on blk0 is minimized 1. each flash chip is logic block (64 * 512b) mapped physical blocks the 64 page in a block has a valid bit: 0: not written, 1 written 2. 3.125% (512 blocks) are assigned as spare blocks flash read flow: ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ error management move the flash block 3. nand mechanism * * * * * * * * * * 2007 - 10 - 19 since eprom may have max 4mb space, it need 32 nand blocks (128k each) while only block zero is guaranteed to be good, we use blk0 as a mapping table between a logic block and a physical block operation steps: 3.1 use external board (e.g. a 8051 board) to establish a logic mapping table on block0, and program mcu code etc to those good blocks. 3.2 put (soldering of use socket) nand on merced board 3.3 power on, the _ flash has a state machine (init _ nm) and a map ram (32 * 8)