EDA和VHDL书上例题.docVIP

1、（1）2选1多路选择器的VHDL描述： ENTITY mux21a IS PORT( a, b : IN BIT ; s : IN BIT; y : OUT BIT ) ; END ENTITY mux21a ; ARCHITECTURE one OF mux21a IS BEGIN y = a WHEN s = 0 ELSE b ; END ARCHITECTURE one （2）2选1多路选择器的VHDL描述（并行语句用布尔方程式表达） ENTITY mux21a IS PORT ( a, b : IN BIT; s : IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS SIGNAL d,e : BIT; BEGIN d = a AND (NOT S); e = b AND s; y = d OR e; END ARCHITECTURE one; （3）2选1多路选择器的VHDL描（用顺序语句） ENTITY mux21a IS PORT ( a, b, s: IN BIT; y : OUT BIT ); END ENTITY mux21a; ARCHITECTURE one OF mux21a IS BEGIN PROCESS (a,b,s) BEGIN IF s = 0 THEN y = a; ELSE y = b; END IF; END PROCESS; END ARCHITECTURE one ; 2、D触发器的VHDL描述 （1）LIBRARY IEEE; USEIEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS PORT(CLK,D:INSTD_LOGIC; Q : OUT STD_LOGIC ); END; ARCHITECTURE bhv OF DFF1 IS SIGNAL Q1 : STD_LOGIC BEGIN PROCESS (CLK) BEGIN IF CLKEVENT AND CLK = 1 THEN Q1 = D; END IF; Q = Q1; END PROCESS; （2）定义变量的D触发器 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY DFF3 IS PORT ( CLK,D1 : IN STD_LOGIC ; Q1 : OUT STD_LOGIC); END ; ARCHITECTURE bhv OF DFF3 IS BEGIN PROCESS (CLK) VARIABLE QQ : STD_LOGIC ; BEGIN IF CLKEVENT AND CLK = 1 THEN QQ := D1 ; END IF; Q1 = QQ; END PROCESS ; END ; （3）定义信号的D触发器 . . . ARCHITECTURE bhv OF DFF3 IS SIGNAL QQ : STD_LOGIC ; BEGIN PROCESS (CLK) BEGIN IF CLKEVENT AND CLK =1 THEN QQ = D1 ; END IF; Q1 = QQ; END PROCESS ; END ; 3、半加器描述： （1）LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY adder IS PORT (a, b : IN STD_LOGIC; co, so : OUT STD_LOGIC); END ENTITY adder; ARCHITECTURE fh1 OF adder is BEGIN so = NOT(a XOR (NOT b)) ; co = a AND b ; END ARCHITECTURE fh1 （2）LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTIT