Field Effect Transistor Abstract - Andrew Lauria（场效应晶体管抽象安德鲁Lauria）.pdf

III-V Field Effect Transistors and the Effect of Gate Channel Length on Shut Off Voltage 1 1 1 1 Andrew Lauria , Michael Fusella , Nyan Aung , and Claire F. Gmachl 1 Princeton University, Department of Electrical Engineering, Equad, Olden St., Princeton, NJ 08544 USA Author email: alauria@princeton.edu Abstract: By successfully constructing and testing several III-V Field Effect Transistors, it is demonstrated that a larger Gate Channel length provides for a shut off voltage with less magnitude. 1. Introduction For this experiment, several III-V Field Effect Transistors (FET) were fabricated. These were built on wafers made of GaAs (bottom) and AlGaAs (top), with a 2-D electron gas in between. This type of transistor, like most others, has similar functionality to a switch. It implements this behavior through the use of three contacts; a drain, source, and gate. The source and drain are connected to opposite sides of the electron gas/wafer. The gate lies on top of the wafer, creating a channel that connects the source and drain with the 2-D electron gas inside. When applying a voltage to the gate, an electric field forms that either attracts or repels electrons. Attraction fills the channel with electrons, enabling the device and allowing current to flow between the source and drain. Repelling electrons has the opposite effect, turning the de