第7篇有限脉冲响应数字滤波器的设计.ppt

应用扩展：基于VHDL语言的FIR数字滤波器设计 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity FirFilterDesign is Generic ( widthIn : integer :=8; widthOut : integer :=32 ); port( reset : in std_logic; clk : in std_logic; clk_ena : in std_logic; dataIn : in std_logic_vector(widthIn-1 downto 0); dataOut : out std_logic_vector(widthOut-1 downto 0)); end FirFilterDesign; Architecture gen of FirFilterDesign is Constant Len :integer := 30 ; type integer_array IS array (NATURAL RANGE ) OF integer; Signal filter_in,output_register : in