基于FPGAUART设计Verilog实现程序.docVIP

module clkdiv (clk,clkout); input clk; //系统时钟 output clkout; //采样时钟输出 reg clkout; reg [24:0] cnt; //分频进程 always @(posedge clk) begin if(cnt == 24d162) begin clkout = 1b1; cnt = cnt + 24d1; end else if(cnt == 24d324) begin clkout = 1b0; cnt = 24d0; end else begin cnt = cnt + 24d1; end end endmodule /*******************发送模块********************************/ module urattx(clk,datain,wrsig,idle,tx); input clk; //UART时钟 input [7:0] datain; //需要发送的数据 input wrsig; //发送命令，上升沿有效 output idle; //线路状态指示，高为线路忙，地为线路空闲 output tx; //发送数据信号 reg idle,tx; reg send; reg wrsigbuf,wrsigrise; reg presult; reg [7:0] cnt; //计数器 parameter paritymode = 1b0; //检测发送命令是否有效 always @(posedge clk) begin wrsigbuf = wrsig; wrsigrise =(~wrsigbuf)wrsig; end always @(posedge clk) begin if(wrsigrise (~idle)) //当发送命令有效且线路为空闲时，启动新的数据发送进程 begin send =1b1; end else if(cnt == 8d176) //一帧资料发送结束 begin send =1b0; end end always @(posedge clk) begin if(send =1b1) begin case(cnt) 8d0: //产生起始位 begin tx = 1b0; idle = 1b1; cnt = cnt + 8d1; end 8d16: begin tx = datain[0]; //发送数据0位 presult = datain[0]^paritymode; idle = 1b1; cnt = cnt + 8d1; end 8d32: begin tx = datain[1]; //发送数据1位 presult = datain[1]^presult; idle = 1b1; cnt = cnt + 8d1; end 8d48: begin tx = datain[2]; //2 presult = datain[2]^presult; idle = 1b1; cnt = cnt + 8d1; end 8d64: begin tx = datain[3]; //3 presult = datain[3]^presult; idle = 1b1; cnt = cnt + 8d1; end 8d80: begin tx = datain[4]; //4 presult = datain[4]^presult; idle = 1b1; cnt = cnt + 8d1; end 8d96: begin tx = datain[5]; //5 presult = datain[5]^presult; idle = 1b1; cnt = cnt + 8d1; end 8d112: begin tx = datain[6]; //6 presult = datain[6]^presult; idle = 1b1; cnt =