High Speed Layout Design Guidelines NXP （高速NXP布局设计指导方针）.pdf

Freescale Semiconductor Document Number: AN2536 Application Note Rev. 2, 04/2006 High Speed Layout Design Guidelines MC9328MX1, MC9328MXL, and MC9328MXS 1 Abstract Contents Design of memory systems becomes more complex as 1 Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Design Consideration . . . . . . . . . . . . . . . . . . 2 the operation frequency increases in a low-power 3 i.MX Case Study . . . . . . . . . . . . . . . . . . . . . . 14 environment. A number of criteria should be considered 4 Design Guidelines on PCB . . . . . . . . . . . . . 20 to achieve maximum system performance under these 5 References . . . . . . . . . . . . . . . . . . . . . . . . . . 23 conditions. The i.MX external memory bus is intended to 6 Revision History . . . . . . . . . . . . . . . . . . . . . . 24 work with PC100 grade memory. Care must be taken in board layout to achieve a system capable of maximum bus rates at low voltage. This document describes the recent investigation into the maximum memory bus frequency of a low-power memory system in terms of stability, capacitive loading, and production margin. This data will be useful to customers in their design of low power high speed memory systems with the i.MX applications processors This document applies to the following i.MX devices, collectively called i.MX throughout: • MC9328MX1 • MC9328MXL • MC9328MXS © Freescale Semiconductor, Inc., 2005, 2006. All rights reserved.