AXI总线学习.docx

PG021S2MM Memory Interface Signals初始值m_axi_s2mm_awaddr(C_M_AXI_S2MM_ADDR_WIDTH-1: 0)O全0写通道地址线m_axi_s2mm_awlen(7:0)O全0写地址通道突发长度数据量-1m_axi_s2mm_awsize(2: 0)O全0突发数据宽度000b = 1 byte (8-bit wide burst)001b = 2 bytes (16-bit wide burst)010b = 4 bytes (32-bit wide burst)011b = 8 bytes (64-bit wide burst).100b = 16 bytes (128-bit wide burst)101b = 32 bytes (256-bit wide burst)m_axi_s2mm_awburst(1:0)O全001b = INCR - Incrementing addressm_axi_s2mm_awaddrO写地址通道写地址有效I从设备准备好接受写地址O写数据通道数据线O字节使能信号O写数据通道最后一个数据标志O写数据通道数据有效标志I从设备准备接收数据就绪I写应答通道响应00=OK10=从设备返回错误11=地址译码错误I写应答通道应答有效标志O准备好接收应答信息寄存器空间支持Scatter/Gather0MM2S DMA控制寄存器4MM2S DMA状态寄存器8MM2S 当前描述符寄存器10hMM2S尾描述符寄存器30hS2MM DMA控制寄存器34S2MM DMA状态寄存器38S2MM 当前描述符寄存器40S2MM 尾描述符寄存器不支持Scatter/Gather0MM2S DMA控制寄存器4MM2S DMA状态寄存器18hMM2S源地址寄存器28MM2S突发长度寄存器30hS2MM DMA控制寄存器34S2MM DMA状态寄存器48S2MM 目的地址寄存器58S2MM 缓冲区长度全部是小端地址模式：DMA控制寄存器：Bit0:0当前DMA操作完成后停止DMA传输或者S/G方式下未完成的命令或传输都被清掉。AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.1启动DMA传输。Bit2:软件复位整个DMA引擎。Bit12:中段完成使能。Bit13:中段完成延时使能。简单模式下无效。Bit14:错误中断时能。Bit23:16中断阈值。最小值为1.每发生一次中断，中断阈值计数器减一，当中断阈值寄存器为0时，DMA引擎向外产生一个中断。简单模式下无效。Bit31:24中断延时寄存器。用来设置中断超时时间。Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout is a mechanism for causing the DMA engine to generate an interrupt after the delay time period has expired. 当中断延时寄存器失效后为了保证仍然可以差生中断。This is used for cases when the interrupt threshold is not met after a period of time, and the CPU desires an interrupt to be generated. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs. Setting thisvalue to zero disablesthe delay timer interrupt.如果在一定的时间内，中断阈值寄存器仍然不到0，而且CPU希望产生一个中断。那么在一个数据包完成后，计数器开始计数直到接收到一个新包后或者超时事件发生后复位计数器。DMA状态寄存器：Bit0:停止状态位。0=DMA运行1=DMA通道停止。从DMA控制寄存器的停止位到状态位反映出来有一段时间。Bit1:DMA通道空闲。Bit3:支持S/G方式否。Bit4:DMA内部错误。Bit5:DMA Slave错误。Bit6:DMA译码错误。Bit8:SG