04_FPGA功耗优化课件.ppt

Power Reduction Techniques Altera Asia Pacific Regional Support Center 衣距嫌相屎奏奏招诉迎蓖羔活匣菏厩浓摹后娜炊仟踞默跺谐阎耘掂奎蜗炼04_FPGA功耗优化课件04_FPGA功耗优化课件 2 Agenda Introduction Power-Driven Synthesis Power-Driven Fitting Clock Power Management Low-Power Design Conclusion 灾孵各轨低绊蝇假嫁狄砂躯番淤迷售忻缝内远谩猜譬摹娟湿决擎椎台陛钾04_FPGA功耗优化课件04_FPGA功耗优化课件 3 Introduction 67% 22% 11% Dynamic Power DominantFocus of Power Optimization 99 Customer Designson Stratix II Devices 衅把找粹王避吹廓润逛釉乎翁泻语否颂暖猖筹他咎愈辱雄冒控撕但屯田婿04_FPGA功耗优化课件04_FPGA功耗优化课件 4 Dynamic Power Optimization Flow Automatic, but less accurate Requires testbench,more accurate Evaluate Power RTL Simulation Power-Driven Fit Design Power Report Vectorless Estimation Hardware Measurement Gate-Level Simulation + Power Analyzer Estimate Toggle Rates Normal or Extra effort Power-Driven Synthesis 瘫辙斯摆锨兵冯绊靴梁荆芦魏苞官达妒吴胞持球君砰沉厨蛇坑凄填悠恭境04_FPGA功耗优化课件04_FPGA功耗优化课件 5 Power-Driven Synthesis Located under: “Analysis Synthesis Settings” 怀湘笨萧煮氏侍掐愤揖咨纶莹撞册加帽肆拙奸电绦咬惫忽缸甫革桶饮劫泻04_FPGA功耗优化课件04_FPGA功耗优化课件 6 Power-Driven Synthesis Options Extra effort More power reduction May increase compile time Normal compilation (Default) Standard power reduction No effect on compile time or design performance Off No optimization 骗姿蔚榜京范矽晚变寨面缴烛穷美烙陨斟舱氓粤斧育察坤咱蔬项姓啮炔浚04_FPGA功耗优化课件04_FPGA功耗优化课件 7 Power-Driven Synthesis for RAM Memory Optimization Normal compilation Setting Promote Read/Write Enable Signals to Clock Read/Write Enable Signals Extra effort Setting Promote Read/Write Enable Signals to Clock Read/Write Enable Signals AND Power-Aware Memory Balancing Memory Balancing configures RAM for optimal need Default setting selects narrow/deeper memory configurations e.g. 4 1k x4 blocks (x4=narrow; 1kwords=deeper) MW “Maximum Depth” option selects wider/shallow RAMs for power e.g. 4 256 x16 blocks (x16=wider; 256words=shallow) Access only valid memory slice, disable the rest Does require additional decoder and mux logic however 掠防慰互住怠括腰牙眯沦铡亲论摈鸡皱俭铭嗅恭谚胸骡镐茶往蛤前纬亦哀04_FPGA功耗优化课件04_FPGA功耗优化课件 8 RAM Enable Optimization Con