VHDL语言应用基础2(描述语句)课件.pptVIP

PART 4 The Basic Statements in VHDL Code ;1. IF Statement;1） IF expression THEN statement; END IF ;【f.e】 IF statement defines the 2-to-1 multiplexer;exercise;Ex: Design a positive-edge-triggered D flip-flop with clear and preset: dffrs port(sset,rreset,d,clk:in bit; q,qb:out bit)； The clear and preset are asynchronous signals, and while “0” have effect. ;ENTITY dffrs IS PORT(sset,rreset,d,clk: IN BIT; q,qb: OUT BIT); END dffrs; ARCHITECTURE ex OF dffrs IS BEGIN PROCESS(sset,rreset,clk); BEGIN ASSERT NOT((sset=‘0’) AND (rreset=‘0’)) REPORT “Control Error” SEVERITY Error; IF (sset=‘0’) AND (rreset=‘1’) THEN q=‘1’; qb=‘0’; ; ELSIF (rreset=‘0’) AND (sset=‘1’)THEN q=‘0’; qb=‘1’; ELSIF(clk’EVENT AND clk=‘1’) THEN q=d; qb=NOT d; END IF; END PROCESS; END ex;;2. CASE Statement; 上述CASE语句中的条件表达式可以有如下4种不同的表示形式：;使用CASE语句时应注意: 条件句的选择值应在表达式的取值范围内. 除非所有条件句中的选择值能完全覆盖case语句中表达式的取值,否则最后一个条件句中的选择必须用“others”表示. case语句中每一条件句的选择值只能出现一次,不能有相同选择值的条件语句出现. case语句执行中必须选中且只能选中所列条件语句中的一条.;【f.e】 An example of a CASE statement used to describe combinational logic is;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL ENTITY mux41 IS PORT ( s1, s2 : in std_logic; a,b,c,d: in std_logic; z: out std_logic); END mux41;;ARCHITECTURE activ OF mux41 IS SIGNAL s :std_logic_vector(1 downto 0); BEGIN S= s1 s2 PROCESS (s1,s2,a,b,c,d) BEGIN IF s =“00” then a=z; ELSIF s=“01” then b=z; ELSIF s=“10” then c=z; ELSE d=z; END IF; END PROCESS; END activ;;exercise;元件外观;LIBRARY IEEE ;;ARCHITECTURE a1 or coder IS;exercise;酮月屁拇寨图膝聂靶大稀困候拄股笨掣章扳常念奎靳步肯蛹炎煎孙翅窜中VHDL语言应用基础2(描述语句)课件VHDL语言应用基础2(描述语句)课件;LIBRARY IEEE ;;ARCHITECTURE a1 or coder IS;IF 与 CASE比较;3. LOOP