尤静-基于可重用技术的介质损耗数据采集系统设计.doc

摘 要 可重用设计方法是以IP复用和IP设计为基础的一种有效的设计方法与先进的设计理念，它将传统的停留在板级设计层面的嵌入式系统硬件设计提升到基于可编程逻辑芯片上的系统级设计。可重用设计方法的引入大大缩短了基于可编程逻辑器件的嵌入式系统设计周期，更为科研院所将独创的算法模型迅速转化为IP核，加以推广应用和知识产权保护提供一个良好的途径，成为设计系统原型的首选方式。 本文将可重设计方法成功地应用到实际科研项目——基于FPGA及IP软核的介质损耗数据采集系统。分析了可重用设计方法在嵌入式系统设计中的重要作用，介绍了电容型设备介质损耗原理，深入分析了影响在线测的因素，并确定了系统设计方案。 在方案设计的基础上，从系统级设计和功能模块级设计角度详细介绍了构成系统的外围电路设计，FPGA内部逻辑的定制，基于NiosⅡ处理器的软件设计并对系统硬件的抗干扰设计进行了简要叙述最终设计并实现了FPGA及IP软核的介质损耗数据采集系统。Abstract Reuse methodology is an efficiency method and advanced idea of chip design, which is based on reusing and design of IP core. It changes the focus of system design from the board-level of embedded system hardware design to the chip-level of programmable logic device based design. The use of reuse methodology does not only decrease the cycle of designing the embedded system based on programmable logic device, but also is a shortcut to transfer a algorithm to an IP core to be protected better and able to be used in lots of fields for academy or research institute. This thesis makes use of reuse methodology to research project——Dielectric loss data collecting system based on FPGA and IP core .The importance of the reuse methodology to the design of embedded system is analyzed first, the principle of the electric capacity equipment dielectric loss examination survey is introduced then, and the factor which affected the on-line monitor is thoroughly analyzed, then the design scheme of the data collecting system is confirmed. On the basis of the scheme design, the periphery hardware designing, the logic customization of FPGA and the software designing based on NiosⅡ was introduced from both the system design and the function module design aspects. Then the anti-jamming principle of hardware design was also simply described in the thesis. The dielectric loss data collecting system based on FPGA and IP core was designed and realized on the basis of above research triumphantly. Keywords: Reuse methodology FPGA IP core Dielectric loss data collection目