pcb制作事项（PCB production matters）.doc

pcb制作事项（PCB production matters） These parts are usually not less than or other signal through another logic processing; is the most typical clock line, usually without any other logic processing, so the delay will be less than other related signal. In the line is in order to make the signal delay difference is maintained in a certain range, to ensure the system to read high speed digital PCB board in the same period the length is in order to make the signal delay difference is maintained in a range to ensure the validity of data read in the same period (the delay difference system more than one clock cycle will be wrong to read the next cycle of the fault data read the next cycle data delay more than one clock cycle), general requirements will be wrong to read the next cycle number according to the general requirements of the delay difference is not more than 1/4 clock cycles per unit length line delay difference is fixed with delay line the length of copper plate layer structure of the line is too long but will clock cycle delay difference does not exceed the validity of the data delay difference of more than one clock cycle, the unit length of the line delay difference is fixed with delay line width, line length The copper thickness, the lamellar structure of the unit length of the line delay difference is fixed, with the length of the delay line, copper plate layer structure, but the line is too long will make the quality of the signal, so the clock termination, but not from serpentine traces of enlarging the inductance of the distributed capacitance and inductance, the signal quality increases distributed capacitance and the inductor signal quality so the clock pin of IC are generally connected to the RC terminal but not an inductance serpentine line, opposite inductance will make harmonic signal in the rising yuan in phase shift caused by the deterioration of the quality of the signal on the contrary, the inductance will make harmonic signal in the yuan rise in