RTL验证工具VCS介绍.pdfVIP

Modifies condition coverage as specified by the argument or arguments: basic Only logical conditions and no multiple conditions. std The default: only logical, multiple, sensitized conditions. full Logical and non-logical, multiple conditions, no sensitized conditions. allops Logical and non-logical conditions. event Signals in event controls in the sensitivity list position are conditions. anywidth Enables conditions that need more than 32 bits. sop Specifies condition SOP coverage. It also tells VCS that when it reads conditional expressions that contain the ^ bitwise XOR and ~^ bitwise XNOR operators, it reduces the expression to negation and logical AND or OR. for Enables conditions in for loops. tf Enables conditions in user defined tasks and functions. You can specify more than one argument. If you do use the + plus delimiter between arguments, for example: -cm_cond basic+allops -cm_tgl mda Enables toggle coverage for Verilog 2001 multidimensional arrays and SystemVerilog unpacked arrays. Not requires for packed SystemVerilog arrays. -P pli.tab Specifies a PLI table file. +libext+ extension Specifies that VCS only search the source files in a Verilog library directory with the specified extension. You can specify more than one extension, separating each extension with the “+” character. For example, +libext++.v specifies searches library files with no extension and library files with the .v extension. Enter this option when you enter the -y option. -v filename Specifies a Verilog library file to search for module definitions.