使用maxplus2用VHDL语言设计EDA数字钟.doc

扫描 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity shch is port(sh,sl,fh,fl,shh,shd:in std_logic_vector(3 downto 0); clk: in std_logic; --con:in std_logic_vector(3 downto 0); smm:out std_logic_vector(5 downto 0); ou:out std_logic_vector(7 downto 0)); end shch; architecture sh_ch of shch is signal tmpe:std_logic_vector(3 downto 0); signal count:std_logic_vector(3 downto 0); signal ouu:std_logic_vector(7 downto 0); begin process(clk) begin if (clkevent and clk=1) then if count=0101 then count=0000; else count=count+1; end if; end if; end process; smm=011111 when count=0101 else 101111 when count=0100else 110111 when count=0011else 111011 when count=0010else 111101 when count=0001else 111110 when count=0000; tmpe=sl when count=0000 else sh when count=0001 else fl when count=0010 else fh when count=0011 else shd when count=0100 else shh when count=0101 ; process(tmpe) begin case tmpe is when 0000=ouu when 0001=ouu when 0010=ouu when 0011=ouu when 0100=ouu when 0101=ouu when 0110=ouu when 0111=ouu when 1000=ouu when 1001=ouu when others=ouu end case; end process; ou=ouu; end sh_ch; 分频器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity jsq_1000 is port(clk:in std_logic; cs: out std_logic); end jsq_1000; architecture jsq of jsq_1000 is begin process(clk) variable count :integer; begin if (clkevent and clk=1) then if count1024 then count:=count+1; cs=0; else count:=0; cs=1; end if; end if; end process; end jsq; 时分秒计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sfsh is port(rst, clk:in std_logic; sh,sl,fh,fl,shh,shd:out std_logic_vector(3 downto 0)); end sfsh; architecture sf_s