cy7c68013的slave fifo的读写速度(极限96mb)（CY7C68013 FIFO slave read write speed (limit 96MB)）.docVIP

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cy7c68013的slave fifo的读写速度(极限96mb)（CY7C68013 FIFO slave read write speed (limit 96MB)）.doc

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cy7c68013的slave fifo的读写速度(极限96mb)（CY7C68013 FIFO slave read write speed (limit 96MB)）

cy7c68013的slave fifo的读写速度(极限96mb)（CY7C68013 FIFO slave read write speed (limit 96MB)） In theory, the limit in slave FIFO mode the value of CY7C68013A is 96 MB/s, this is the ideal state Reference 1: Achieving a Local Transfer Rate of 96MB/s in FX2 Title: Achieving a Local Transfer Rate of 96MB/s in FX2 Question: How can the local transfer rate of 96 MB/s be achieved? Response: The burst rate of 96MB/s can be achieved by running the Slave FIFOs at 48 MHz (internal or external clock while asserting SLWR), or SLRD/SLOE for the entire data burst phase. Assuming active low polarity signals, when writing to the Slave FIFOs, SLWR should be held low as each word is clocked on the rising edge of IFCLK. The case is similar for reading from the Slave FIFOs SLOE/SLRD should be held low; as each new word is read on every rising edge of IFCLK. The technical reference manual assumes a conservative approach as the examples show a word being clocked on every other IFCLK edge. This is for systems that may not be able to abide by the setup and hold times required for a burst phase like whats described above. Clocking a word on every other edge would then reduce the effective burst rate to 48 MB/s. Notes: 1) FX2 has the ability to have the FIFO flags assert one word prior to the FIFO becoming full, and one word prior to the FIFO becoming empty. This give the external master additional time to check the FIFO status flags. 2) To achieve the 96MBs, the control signals will have to be active while each word is clocked on the rising edge of IFCLK. 3) The endpoints and FIFOs share the same physical memory space. Often youll see them referred to as endpoint FIFOs because they exhibit a dual personality. There are basically two domains the endpoint FIFOs reside in, the USB domain, and the peripheral interface domain. FX2 is able to switch clock domains to pass the packet pointers from one domain to the other, thus seemingly able to connect the USB domain to the peripheral interface domain. Th