TimeQuest使用教程(中文版)分析.pptVIP

* * * * * Speaker Note: “no sep model for rise / fall means that the slower is defined for slow corner model then the fast model (for stratix is defined by scaling that model. This means that the actual fastest path (rise or fall) may not be captured. Guardbanding is very important to catch this. * * * * Relative to REG2 * “Double-clocking” is when data arrival time is so low when compared to the clock arrival time that it is clocked through two subsequent register stages during one clock cycle * The design used for this exercise (shown on the following page) multiplies two sets of 8-bit data inputs: din_a * din_b and din_x * din_y. Along with this data input, the design also receives a board clock named clk_in_100mhz running at 100 MHz and an asynchronous reset named reset. To save on multiplier space, the data is time-domain multiplexed through a single multiplier running at twice the clock speed (200 MHz). All clocks for the design are generated by a PLL called main_pll with 3 output clocks. A 100 MHz PLL output called c100 is used to reduce clock tree delay to internal registers. A 200 MHz PLL output called c200 drives the multiplier at twice the input frequency. A second 100 MHz output from the PLL called c100_out drives the output port, clkout. The resulting data output named multout_ab and multout_xy is center-aligned with clkout (by means of the PLL) and then sent off-chip to another device on the board. * * * * TimeQuest的缺省公式是正确的——多周期路径的设置不应影响Hold Time的检查。究其原因，多周期路径是为了解决信号传播太慢的问题，慢到一个周期都不够，所以要把Setup Time的检查往后推几个周期——扩大Setup Time检查的时间窗口。而Hold Time检查信号是否传播得太快，如果把检查时刻往后推，就缩小了Hold Time检查的时间窗口。 ? “信号跳变抵达窗口”：对Latch寄存器来说，从previous时钟对应的Hold Time开始，到current时钟对应的Setup Time结束。 “信号电平采样窗口”：对Latch寄存器来说，从current时钟对应的Setup Time 开始，到current时钟对应的Hold Time结束。 ? Launch寄存器必须保证驱动的信号跳变到达Latch寄存器的时刻恰好处于“信号跳变抵达窗口”内，才能保证不破坏Latch寄存器的“信号电平采样窗口”。 时序检查的目的就是确认信号跳变发生在“信号跳变抵达窗口”内，而不会发生在“信号电平采样窗口”内。 ? 多周期路径的设置是通过延后Setup Time检查的时刻，扩大了“信号跳变抵达窗口”，放松了时序约束。通过窗口的概念，也很容易理解延后Hold Time，就会