Xilinx官方verilog指南.pdf

Chapter 7 Verilog Language Support This chapter contains the following sections. Introduction Behavioral Verilog Features Structural Verilog Features Parameters Verilog Limitations in XST Verilog Meta Comments Language Support Tables Primitives Verilog Reserved Keywords For detailed information about Verilog design constraints and options, refer to the Design Constraints chapter. For information about the Verilog attribute syntax, see the Verilog Meta Comment Syntax section of the Design Constraints chapter. For information on setting Verilog options in the Process window of the Project Navigator, refer to the Setting Global Constraints and Options section of the Design Constraints chapter. Introduction Complex circuits are commonly designed using a top down methodology. Various specification levels are required at each stage of the design process. As an example, at the architectural level, a specification may correspond to a block diagram or an Algorithmic State Machine (ASM) chart. A block or ASM stage corresponds to a register transfer block (for example register, adder, counter, multiplexer, glue logic, finite state machine.) where the connections are N-bit wires. Use of an HDL language like Verilog allows expressing notations such as ASM charts and circuit diagrams in a computer language. Verilog provides both behavioral and structural language structures which allow expressing design objects at high and low levels of abstraction. Designing hardware with a language like Verilog allows usage of software concepts such as parallel processing and object-oriented programming. Verilog has a syntax similar to C and Pascal, and is supported by X