香港大学Ke_Xu_h264_FPGA.pdfVIP

Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2009, Article ID 425173, 17 pages doi:10.1155/2009/425173 Research Article Low-Power Bitstream-Residual Decoder for H.264/AVC Baseline Profile Decoding Ke Xu and Chiu-Sing Choy Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong Correspondence should be addressed to Ke Xu, kexu@.hk Received 11 July 2009; Revised 21 October 2009; Accepted 2 December 2009 Recommended by Leonel Sousa We present the design and VLSI implementation of a novel low-power bitstream-residual decoder for H.264/AVC baseline profile. It comprises a syntax parser, a parameter decoder, and an Inverse Quantization Inverse Transform (IQIT) decoder. The syntax parser detects and decodes each incoming codeword in the bitstream under the control of a hierarchical Finite State Machine (FSM); the IQIT decoder performs inverse transform and quantization with pipelining and parallelism. Various power reduction techniques, such as data-driven based on statistic results, nonuniform partition, precomputation, guarded evaluation, hierarchical FSM decomposition, TAG method, zero-block skipping, and clock gating , are adopted and integrated throughout the bitstream- residual decoder. With innovative architecture, the proposed design is able to decode QCIF video sequences of 30 fps at a clock rate as low as 1.5 MHz. A prototype H.264/AVC baseline decoding chip utilizing the proposed decoder is fabricated in UMC 0.18 μm 1P6M CMOS technology. The proposed design is measured under 1 V ∼ 1.8 V supply with 0.1 V step. It dissipates 76μW at 1 V and 253 μW at 1.8 V. Copyright © 2009 K. Xu and C.-S. Choy. This is an open access article distributed under the Creative Commons Attribution License, whic